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CD4018BMS
November 1994
CMOS Presettable Divide-By- "N" Counter
Description
CD4018BMS types consist of 5 Johnson-Counter stages, buffered Q outputs from each stage, and counter preset control gating. CLOCK, RESET, DATA, PRESET ENABLE, and 5 individual JAM inputs are provided. Divide by 10, 8, 6, 4, or 2 counter configurations can be implemented by feeding the Q5, Q4, Q3, Q2, Q1 signals, respectively, back to the DATA input. Divide-by-9, 7, 5, or 3 counter configurations can be implemented by the use of a CD4011B to gate the feedback connection to the DATA input. Divide-by functions greater than 10 can be achieved by use of multiple CD4018BMS units. The counter is advanced one count at the positive clock-signal transition. Schmitt Trigger action on the clock line permits unlimited clock rise and fall times. A high RESET signal clears the counter to an all-zero condition. A high PRESET-ENABLE signal allows information on the JAM inputs to preset the counter. Anti-lock gating is provided to assure the proper counting sequence. The CD4018BMS is supplied in these 16-lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack H4T H1F H6W
Features
* High Voltage Type (20V Rating) * Medium Speed Operation 10MHz (typ.) at VDD - VSS = 10V * Fully Static Operation * 100% Tested for Quiescent Current at 20V * Standardized Symmetrical Output Characteristics * 5V, 10V and 15V Parametric Ratings * Maximum Input Current of 1a at 18V Over Full Package-Temperature Range; - 100nA at 18V and 25oC * Noise Margin (Over Full Package Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V * Meets All Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of `B' Series CMOS Devices"
Applications
* Fixed and Programmable Divided- By-10, 9, 8, 7, 6, 5, 4, 3, 2 Counters * Fixed and Programmable Counters Greater Than 10 * Programmable Decade Counters * Divide-By- "N" Counters/Frequency Synthesizers * Frequency Division * Counter Control/Timers
Functional Diagram
JAM INPUTS "2" "1" 2 3 "3" 7 9 "4" "5" 12 16 VDD
Pinout
CD4018BMS TOP VIEW
DATA 1 JAM 1 2 JAM 2 3 Q2 4 Q1 5 Q3 6 JAM 3 7 VSS 8 16 VDD 15 RESET
PRESET 10 ENABLE CLOCK DATA RESET 14 1 15
5 4 6
Q1 Q2 Q3 BUFFERED OUT
11 Q4 13 Q5
14 CLOCK 13 Q5 12 JAM 5 11 Q4 10 PRESET ENABLE 9 JAM 4 8 VSS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999
File Number
3298
7-350
Specifications CD4018BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 1/32 Inch (1.59mm 0.79mm) from case for 10s Maximum
Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . . ja jc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2 VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Output Voltage Output Voltage Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) N Threshold Voltage P Threshold Voltage Functional VOL15 VOH15 IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VNTH VPTH F VDD = 15V, No Load VDD = 15V, No Load (Note 3) VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Input Voltage Low (Note 2) Input Voltage High (Note 2) Input Voltage Low (Note 2) Input Voltage High (Note 2) VIL VIH VIL VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V 3 1, 2, 3 1, 2, 3 1 1 1 1 1 1 1 1 1 7 7 8A 8B 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 +25oC, LIMITS TEMPERATURE +25
oC
PARAMETER Supply Current
SYMBOL IDD
CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND
MIN -100 -1000 -100 -
MAX 10 1000 10 100 1000 100 50 -0.53 -1.8 -1.4 -3.5 -0.7 2.8
UNITS A A A nA nA nA nA nA nA mV V mA mA mA mA mA mA mA V V V
+125oC -55oC +25oC +125o C -55oC +25oC +125oC -55oC +25oC, +125oC, -55oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +125oC -55oC +125oC, -55oC
+25oC, +125oC, -55oC 14.95 0.53 1.4 3.5 -2.8 0.7
VOH > VOL < VDD/2 VDD/2
3.5 11
1.5 4 -
V V V V
+25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC
NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs
3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max.
7-351
Specifications CD4018BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS TEMPERATURE 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 +25oC +125oC, -55oC +25oC +125oC, -55oC +25 C +125oC, -55oC
o
LIMITS MIN MAX 400 540 550 743 550 743 UNITS ns ns ns ns ns ns
PARAMETER Propagation Delay Clock To Q Propagation Delay Preset To Q Propagation Delay Reset To Q NOTES:
SYMBOL TPHL1 TPLH1 TPHL2 TPLH2 TPLH3
CONDITIONS (NOTE 1) VDD = 5V, VIN = VDD or GND
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS VDD = 5V, VIN = VDD or GND VDD = 10V, VIN = VDD or GND VDD = 15V, VIN = VDD or GND Output Voltage Output Voltage Output Voltage Output Voltage Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) Input Voltage Low Input Voltage High Propagation Delay Clock To Q Propagation Delay Preset To Q Propagation Delay Reset to Q VOL VOL VOH VOH IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VIL VIH TPHL1 TPLH1 TPHL2 TPLH2 TPLH3 VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD =15V, VOUT = 13.5V VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V NOTES 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 TEMPERATURE -55oC, +25oC +125oC -55oC, +25oC +125oC -55oC, +25oC +125oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC +25oC +25oC +25oC +25oC +25oC 4.95 9.95 0.36 0.64 0.9 1.6 2.4 4.2 7 -0.36 -0.64 -1.15 -2.0 -0.9 -1.6 -2.4 -4.2 3 180 130 250 180 250 180 V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA V V ns ns ns ns ns ns 50 mV MIN MAX 5 150 10 300 10 600 50 UNITS A A A A A A mV
7-352
Specifications CD4018BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Transition Time Maximum Clock Input Frequency SYMBOL TTHL TTLH FCL CONDITIONS VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V Minimum Data Setup Time TS VDD = 5V VDD = 10V VDD = 15V Minimum Data Hold Time TH VDD = 5V VDD = 10V VDD = 15V Minimum Clock Pulse Width TW VDD = 5V VDD = 10V VDD = 15V Minimum Preset/Reset Removal Time TREM VDD = 5V VDD = 10V VDD = 15V Minimum Preset/Reset Pulse Width TW VDD = 5V VDD = 10V VDD = 15V Input Capacitance NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional Propagation Delay Time SYMBOL IDD VNTH VTND VTP VTPD F TPHL TPLH CONDITIONS VDD = 20V, VIN = VDD or GND VDD = 10V, ISS = -10A VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VSS = 0V, IDD = 10A VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND VDD = 5V 1, 2, 3, 4 +25oC NOTES 1, 4 1, 4 1, 4 1, 4 1, 4 1 TEMPERATURE +25oC +25oC +25oC +25oC +25oC +25oC MIN -2.8 0.2 VOH > VDD/2 MAX 25 -0.2 1 2.8 1 VOL < VDD/2 1.35 x +25oC Limit UNITS A V V V V V ns CIN Any Input NOTES 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2 TEMPERATURE +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25 C +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC
o
MIN 3 7 8.5 -
MAX 100 80 40 12 6 140 80 60 160 70 50 80 30 20 160 70 50 7.5
UNITS ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF
NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
3. See Table 2 for +25oC limit. 4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC PARAMETER Supply Current - MSI-2 Output Current (Sink) SYMBOL IDD IOL5 1.0A 20% x Pre-Test Reading DELTA LIMIT
7-353
Specifications CD4018BMS
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC PARAMETER Output Current (Source) SYMBOL IOH5A DELTA LIMIT 20% x Pre-Test Reading
TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Initial Test (Pre Burn-In) Interim Test 1 (Post Burn-In) Interim Test 2 (Post Burn-In) PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A Group B Subgroup B-5 Subgroup B-6 Group D MIL-STD-883 METHOD 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 Sample 5005 Sample 5005 Sample 5005 Sample 5005 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas 1, 7, 9 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3 Subgroups 1, 2, 3, 9, 10, 11 IDD, IOL5, IOH5A READ AND RECORD IDD, IOL5, IOH5A IDD, IOL5, IOH5A IDD, IOL5, IOH5A
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION MIL-STD-883 METHOD 5005 TEST PRE-IRRAD 1, 7, 9 POST-IRRAD Table 4 READ AND RECORD PRE-IRRAD 1, 9 POST-IRRAD Table 4
CONFORMANCE GROUPS Group E Subgroup 2
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION Static Burn-In 1 Note 1 Static Burn-In 2 Note 1 Dynamic BurnIn Note 1 Irradiation Note 2 NOTE: 1. Each pin except VDD and GND will have a series resistor of 10K 5%, VDD = 18V 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V 0.5V OPEN 4 - 6, 11, 13 4 - 6, 11, 13 4 - 6, 11, 13 GROUND 1 - 3, 7 - 9, 10, 12, 14, 15 8 2, 8, 9, 15 8 VDD 16 1 - 3, 7, 9, 10, 12, 14 - 16 1, 3, 12, 16 1 - 3, 7, 9, 10, 12, 14 - 16 4 - 6, 11, 13 7, 14 10 9V -0.5V 50kHz 25kHz
7-354
CD4018BMS Logic Diagram
RESET
*
15
R PE PE R 2
PRESET ENABLE
*
10
*
J1
R
3
*
J2
R
7
*
J3
R
9
*
J4
R
DATA
12 * J5
*
1
D1 Q1 CL Q1
D2 Q2 CL Q2
D3 Q3 CL Q3
D4 Q4 CL Q4
D5 Q5 CL Q5
CLOCK
PE PE
PE PE
PE PE
PE PE
PE PE
*
14
5
Q1
4
Q2
6
Q3
11 Q4
13 Q5
FIGURE 1. LOGIC DIAGRAM
PE CL CL CL CL DN VDD p n CL R JN PE p n PE p n CL p n CL CL p n CL QN QN
CL p n CL
VSS *ALL INPUTS PROTECTED BY CMOS INPUT PROTECTION NETWORK
FIGURE 2.
DETAIL OF A TYPICAL STAGE
7-355
CD4018BMS Typical Performance Characteristics
AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
30 25 20 15 10 5
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 7.5 5.0 2.5 10V
10V
5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V
FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5
0
0 -5 -10 -15
0
0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
-10V
-20 -25
-10V
-10
-15V
-30
-15V
-15
FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS
FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS
PROPAGATION DELAY TIME (tPHL, tPLH) (ns)
AMBIENT TEMPERATURE (TA) = +25oC TRANSITION TIME (tTHL, tTLH) (ns)
AMBIENT TEMPERATURE (TA) = +25oC
300 SUPPLY VOLTAGE (VDD) = 5V 200
200 SUPPLY VOLTAGE (VDD) = 5V
150
100 10V 50 15V
10V 100 15V
0 0
20
40 60 80 100 LOAD CAPACITANCE (CL) (pF)
0
20
40
60
80
100
LOAD CAPACITANCE (CL) (pF)
FIGURE 7. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE
FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (CLOCK TO Q)
7-356
CD4018BMS Typical Performance Characteristics (Continued)
PROPAGATION DELAY TIME (tPHL, tPLH) (ns)
4
AMBIENT TEMPERATURE (TA) = +25oC POWER DISSIPATION (PD) (W) 10
4
2 8 6 4 2
SUPPLY VOLTAGE (VDD) = 15V 10V 10V
300 SUPPLY VOLTAGE (VDD) = 5V 200 10V
103
8 6 4 2
5V CL = 50pF CL = 15pF
102
100 15V
8 6 4 2
10
2 4 68
AMBIENT TEMPERATURE (TA) = +25oC
2 4 68 2 4 68 2 4 68 2 4 68
0
20
40
60
80
100
1
LOAD CAPACITANCE (CL) (pF)
102 102 103 104 INPUT FREQUENCY (fCL) (HZ)
105
FIGURE 9. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (RESET TO Q)
FIGURE 10. TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF CLOCK INPUT FREQUENCY
Timing Diagram
("DATA" INPUT TIED TO Q5 FOR DECADE COUNTER CONFIGURATION) CLOCK RESET PRESET JAM 1 JAM 2 JAM 3 JAM 4 JAM 5 Q1 Q2 Q3 Q4 Q5 DON'T CARE UNTIL PRESET "GOES HIGH"
FIGURE 11. TIMING DIAGRAM
7-357
CD4018BMS
EXTERNAL CONNECTIONS FOR DIVIDE BY 10, 9, 8, 7, 6, 5, 4, 3, OPERATION
CL J1 J2 J3 J4 J5
No External Components DIVIDE BY 10 Q5 Connected Back To "Data" Required DIVIDE BY 8 DIVIDE BY 6 DIVIDE BY 4 DIVIDE BY 2 Q4 Connected No External Components Back To "Data" Required Q3 Connected No External Components Back To "Data" Required Q2 Connected No External Components Back To "Data" Required Q1
D R Q3 Q4
CL / 7
DIVIDE BY 9 1/2 CD4011B Q4 CONNECTED BACK TO "DATA" (SKIPS "ALL-I's" STATE) Q5 DIVIDE BY 7 1/2 CD4011B Q3 CONNECTED BACK TO "DATA" (SKIPS "ALL-I's" STATE) Q4 DIVIDE BY 5 1/2 CD4011B Q2 CONNECTED BACK TO "DATA" (SKIPS "ALL-I's" STATE) Q3 DIVIDE BY 3 1/2 CD4011B Q1 CONNECTED BACK TO "DATA" (SKIPS "ALL-I's" STATE) Q2
FIGURE 13. EXAMPLE OF DIVIDE BY 7
Chip Dimensions and Pad Layout
FIGURE 12. EXTERNAL CONNECTIONS FOR DIVIDE BY 10, 9, 8, 7, 6, 5, 4, 3, 2 OPERATION
Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch)
METALLIZATION:
Thickness: 11kA - 14kA,
AL.
PASSIVATION: 10.4kA - 15.6kA, Silane BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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